An arithmetic processing apparatus is a semiconductor chip of a highly integrated circuit called a CPU (Central Processing Unit) or a processor. Recent processors tend to be multi-cored with multiple processor cores as arithmetic processing circuits.
As for the multi-cored processor, a processor has been developed which has multiple core memory groups (CMGs) each including multiple cores, a last level cache (hereinafter referred to as an LL cache) shared by the multiple cores, and a memory access control circuit (MAC).
In the processor having the multiple CMGs, in order to maintain a cache coherency between the CMGs, each CMG includes a directory cache having data possession information indicating whether or not the data of memories managed by the own CMG and the other CMGs are possessed in an L2 cache. When a cache miss occurs in response to a memory access request, each CMG refers to the directory cache to determine whether the own CMG or the other CMGs possesses the data of the memory access request in a cache. When any of the other CMGs possesses the data, the own CMG issues a data request to the other CMG to export the data in the L2 cache.
In the processor having the multiple CMGs, each CMG sets a home agent between the LL cache and the memory access controller, and sets the directory cache recording the possession information indicating whether or not the data of memories managed by the own CMG are possessed by the own CMG and the other CMGs, in the home agent. In this manner, when the directory cache having the data possession information of all the CMGs is set in the home agent in each CMG, a memory access request from all the CMGs is input to a pipeline circuit of the home agent to determine whether or not the home agent issues a data export request to another CMG.
However, as the recent evolution of multicore has been further progressed, the number of CMGs has increased, which imposes a heavy burden on the circuit scale of the directory cache in the home agent set in each CMG and the number of processes performed by the pipeline of the home agent.
Related techniques are disclosed in, for example, International Publication Pamphlet No. WO2007/099643.